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ksz8041nl/rnl 10base - t/100base - tx physical layer transceiver revision 1.5 micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com february 4, 2015 revision 1.5 general description the ksz8041nl is a single supply 10base - t/100base - tx physical layer transceiver, which provides mii/rmii interfaces to transmit and receive data. a unique mixed signal design extends signaling distance while reducing power consumption. hp auto mdi/mdi - x provides the most robust solution for eliminating the need to differentiate betwee n crossover and straight - through cables. the ksz8041nl represents a new level of features and performance and is an ideal choice of physical layer transceiver for 10base - t/100base - tx applications. the ksz8041rnl is an enhanced rmii version of the ksz8041 nl that does not require a 50mhz system clock. it uses a 25mhz crystal for its input reference clock and outputs a 50mhz rmii reference clock to the mac. the ksz8041nl and ksz8041rnl are available in 32 - pin, lead - free qfn packages (s ee ordering information ). datasheets and support documentation are available on micrels web site at: www.micrel.com . functional diagram 10/100 pulse shaper nrz/nrzi mlt3 encoder parallel/serial manchester encoder 4b/5b encoder scrambler parallel/serial transmitter tx+ tx- adaptive eq base line wander correction mlt3 decoder nrzi/nrz clock recovery 4b/5b decoder descrambler serial/parallel auto negotiation 10base-t receiver manchester decoder serial/parallel pll led driver rmii rx- rx+ xi xo led1 led0 power down power saving txd1 txd0 rxd1 tx_en mdc mdio rx_er rxd0 rext ref_clk crs_dv rst# intrp ksz8041nl ksz8041rnl downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 2 revision 1.5 features ? single - chip 10base - t/100base - tx physical layer solution ? fully compliant to ieee 802.3u s tandard ? low power cmos design, power consumption of <180mw ? hp auto mdi/mdi - x for reliable detection and correction f or straight - through and crossover cables with disable and enable option ? robust operation over standard cables ? power down and power saving modes ? mii interface support (ksz8041nl only) ? rmii interface support with external 50mhz system clock (ksz8041nl only) ? rmii interface support with 25mhz crystal/clock input and 50mhz reference clock output to mac (ksz8041rnl only) ? miim (mdc/mdio) management bus to 6.25mhz for rapid phy register configuration ? interrupt pin option ? programmable led outputs for link, activity and speed ? esd rating (6kv) ? single power supply (3.3v) ? built - in 1.8v regulator for core ? available in 32 - pin 5mm 5mm qfn package applications ? printer ? lom ? game c onsole ? iptv ? ip p hone ? ip set - top b ox downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 3 revision 1.5 ordering information for the device marking (second column in the ordering informat ion table), the fifth character of line 3 indicates whether the device has gold wire bonding or silver wire bonding, as follows: ? gold wire bonding: the letter s is not present as the fifth character of line 3. ? silver wire bonding: the letter s is present as the fifth character of line 3. for line three, the presence or non-presence of the letter s is preceded by yyww, indicating the last two digits of the year and the two digits work week for the chip date code, and is follo wed by xxx, indicating the chip revision and assembly site. part number device marking package temperature range wire bonding description ksz8041nl ksz8041nl yywwxxx 32-pin qfn 0c to 70c gold mii, commercial temperature, gold wire bonding, 32-pin qfn, pb-free spnz801162 ( 1 ) ksz8041nl yyww s xxx 32-pin qfn 0c to 70c silver mii, commercial temperature, silver wire bonding, 32-pin qfn, pb-free ksz8041nli ksz8041nli yywwxxx 32-pin qfn ? 40c to 85c gold mii, industrial temperature, gold wire bonding, 32-pin qfn, pb-free spny801162 ( 1 ) ksz8041nli yyww s xxx 32-pin qfn ? 40c to 85c silver mii, industrial temperature, silver wire bonding, 32-pin qfn, pb-free ksz8041nl am ( 1 ) ksz8041nl am yywwxxx 32-pin qfn ? 40c to 85c gold mii, industrial temperature, gold wire bonding, 32-pin qfn, pb-free, automotive qualified device. ksz8041rnlu ( 1 ) ksz8041 rnlu yywwxxx 32-pin qfn ? 40c to 85c gold rmii with 50mhz clock output, industrial temperature, gold wire bonding, 32-pin qfn, pb-free, automotive qualified device. ksz8041rnl ksz8041rnl yywwxxx 32-pin qfn 0c to 70c gold rmii with 50mhz clock output, commercial temperature, gold wire bonding, 32-pin qfn, pb-free spnz801164 ( 1 ) ksz8041rnl yyww s xxx 32-pin qfn 0c to 70c silver rmii with 50mhz clock output, commercial temperature, silver wire bonding, 32-pin qfn, pb-free ksz8041rnli ksz8041rnli yywwxxx 32-pin qfn ? 40c to 85c gold rmii with 50mhz clock output, industrial temperature, gold wire bonding, 32-pin qfn, pb-free spny801164 ( 1 ) ksz8041rnli yyww s xxx 32-pin qfn ? 40c to 85c silver rmii with 50mhz clock output, industrial temperature, silver wire bonding, 32- pin qfn, pb-free note: 1. contact factory for availability. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 4 revision 1.5 revision history revision date summary of changes 1.0 10/13/06 data sheet created. 1.1 4/27/07 added maximum mdc clock speed. added 40k 30% to n ote 1 of pin description and strapping options tables for internal pull - ups/pull - downs. changed model number in register 3h C phy identifier 2. changed polarity (swapped definition) of duplex strapping pin. removed duplex strapping pin update to register 4h C auto - negotiation advertisement bits [8, 6]. set disab le power saving as the default for register 1fh bit [10]. corrected led1 (pin 31) definition for activity in led mode 01. added symbol error to mii/rmii receive error description and register 15h C rxer counter. added a 100pf capacitor on rext (pin 10) in pin description table. 1.2 7/18/08 added automotive qualified part number to ordering information. added maximum case temperature. added thermal resistance ( jc ). added chip maximum current consumption. 1.3 12/11/09 added automotive qualified part number, ksz8041nl eam, to ordering information. changed mdio hold time (min) from 10ns to 4ns. added led drive current. renamed register 3h bits [3:0] to manufacturers revision number and changed default value to indicates silicon revision. updated rmii output delay for crsdv and rxd[1:0] output pins. added support for asymmetric pause in register 4h bit [11]. added control bits for 100base - tx preamble restore (register 14h bit [7]) and 10base - t preamble restore (register 14h bit [6]). changed strapping pin definition for config[2:0] = 100 from pcs loopback to mii 100mbps pr eamble restore. corrected mii timing for t rlat , t crs1 , t crs2 . added ksz8041rnl device and updated entire data sheet accordingly. 1.4 1/19/10 removed part number (ksz8041nl eam) from ordering information. removed chip maximum current consumption. 1.5 2/2/15 added automotive qualified part number, ksz8041rnlu. changed vddpll_1.8 (pin 2) decoupling capacitor value from 10 f to 1.0 f. specified minimum 250s rise time for 3.3v inp ut supply voltages (v ddio_3.3, v dda_3.3 ). add the part numbers of the silver wire bonding in ordering information . downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 5 revision 1.5 contents list of figures .......................................................................................................................................................................... 7 list of tables ........................................................................................................................................................................... 8 pin configuration ? ksz8041nl ............................................................................................................................................. 9 pin description ? ksz8041nl .............................................................................................................................................. 10 strapping options ? ksz8041nl .......................................................................................................................................... 14 pin configuration ? ksz8041rnl ........................................................................................................................................ 15 pin description ? ksz8041rnl ............................................................................................................................................ 16 strapping options ? ksz8041rnl ....................................................................................................................................... 19 functional description ........................................................................................................................................................... 20 100base - tx transmit ........................................................................................................................................................ 20 100base - tx receive ......................................................................................................................................................... 20 pll clock synthesizer ...................................................................................................................................................... 20 scrambler/de - scrambler (100base - tx only) .................................................................................................................... 20 10base - t transmit ............................................................................................................................................................ 20 10base - t r eceive ............................................................................................................................................................. 21 sqe and jabber function (10base - t only) ...................................................................................................................... 21 auto - negotiation ................................................................................................................................................................ 21 mii management (miim) interface ..................................................................................................................................... 23 interrupt (intrp) ............................................................................................................................................................... 23 mii data interface (ksz8041nl only) ............................................................................................................................... 23 mii signal definition (ksz8041nl only) ............................................................................................................................ 24 transmit clock (txc) .................................................................................................................................................... 24 transmit enable (txen) ................................................................................................................................................ 24 transmit data [3:0] (txd[3:0]) ....................................................................................................................................... 24 receive clock (rxc) ..................................................................................................................................................... 24 receive data valid (rxdv) ........................................................................................................................................... 25 receive data [3:0] (rxd[3:0]) ....................................................................................................................................... 25 receive error (rxer) .................................................................................................................................................... 25 carrier sense (crs) ...................................................................................................................................................... 25 collision (col) ............................................................................................................................................................... 25 reduced mii (rmii) data interface ................................................................................................................................ 25 rmii signal definition ........................................................................................................................................................ 26 reference clock (ref_clk) ......................................................................................................................................... 26 transmit enable (tx_en) .............................................................................................................................................. 26 transmit data [1:0] (txd[1:0]) ....................................................................................................................................... 26 carrier sense/receive data valid (crs_dv) ............................................................................................................... 27 receive data [1:0] (rxd[1:0]) ....................................................................................................................................... 27 receive error (rx_er) .................................................................................................................................................. 27 collision detection ......................................................................................................................................................... 27 downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 6 revision 1.5 rmii signal diagram ......................................................................................................................................................... 27 straight cable ................................................................................................................................................................ 29 crossover cable ............................................................................................................................................................ 29 power manage ment .......................................................................................................................................................... 30 power saving mode ....................................................................................................................................................... 30 power - down mode ............................................................................................................................................................ 30 reference clock connection options ............................................................................................................................... 30 reference circuit for power and ground connections ..................................................................................................... 31 register map ......................................................................................................................................................................... 32 register description .............................................................................................................................................................. 33 absolute maximum ratings .................................................................................................................................................. 42 operating ratings ................................................................................................................................................................ . 42 electrical characteristics ....................................................................................................................................................... 42 timing diagrams ................................................................................................................................................................... 44 mii transmit timing (10base - t) ........................................................................................................................................ 45 mii receive timing (10base - t) ......................................................................................................................................... 46 mii transmit timing (100base - tx) ................................................................................................................................... 47 mii receive timing (100base - tx) .................................................................................................................................... 48 rmii timing ....................................................................................................................................................................... 49 auto - negotiation timing .................................................................................................................................................... 50 mdc/mdio timing ............................................................................................................................................................ 51 power - up/reset timing .................................................................................................................................................... 52 reset circuit .......................................................................................................................................................................... 53 reference circuits for led strapping pins ........................................................................................................................... 54 selection of isolation transformer ........................................................................................................................................ 55 selection of reference crystal .............................................................................................................................................. 55 package information and recommended landing pattern .................................................................................................. 56 downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 7 revision 1.5 list of figures figure 1. auto - negotiation flow chart ................................................................................................................................ 22 figure 2. ksz8041nl rmii interface .................................................................................................................................. 27 figure 3. ksz8041rnl rmii interface ............................................................................................................................... 28 figure 4 . typical straight cable connection ...................................................................................................................... 29 figure 5. typical crossover cable connection .................................................................................................................. 29 figure 6. 25mhz crystal/oscillator reference clock ......................................................................................................... 30 figure 7. 50mhz oscillator reference clock fo ksz8041nl rmii mode .......................................................................... 30 figure 8. ksz8041nl/rnl power and ground connections ............................................................................................. 31 figure 9. mii sqe timing (10base - t) ................................................................................................................................ 44 figure 10. mii transmit timing (10base - t) .......................................................................................................................... 45 figure 11. mii receive timing (10base - t) ........................................................................................................................... 46 figure 12. mii transmit timing (100base - tx) ...................................................................................................................... 47 figure 13. mii receive timing (100base - tx) ....................................................................................................................... 48 figure 14. rmii timing C data received from rmii ............................................................................................................. 49 figure 15. rmii timing C data input to rmii ........................................................................................................................ 49 figure 16. auto - negotiation fast link pulse (flp) ti ming .................................................................................................. 50 figure 17. mdc/mdio timing ............................................................................................................................................... 51 figure 18. power - up/reset timing ....................................................................................................................................... 52 figure 19. recommended reset circuit ............................................................................................................................... 53 figure 20. recommended reset circuit for interfacing with cpu/fpga reset output. ...................................................... 53 figure 21. reference circuits for led strapping pins ......................................................................................................... 54 downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 8 revision 1.5 list of tables table 1. mii management frame format ........................................................................................................................... 23 table 2. mii signal definition .............................................................................................................................................. 24 table 3. rmii signal description C ksz8041nl ................................................................................................................. 26 table 4. rmii signal description C ksz8041rnl .............................................................................................................. 26 table 5. mdi/mdi - x pin description ................................................................................................................................... 28 table 6. ksz8041nl/rnl power pin description .............................................................................................................. 31 table 7. mii sqe timing (10base - t) parameters .............................................................................................................. 44 table 8. mii transmit timing (10base - t) parameters ....................................................................................................... 45 table 9. mii receive timing (10base - t) parameters ........................................................................................................ 46 table 10. mii transmit timing (100base - tx) parameters ................................................................................................... 47 table 11. mii receive timing (100base - tx) parameters .................................................................................................... 48 table 12. rmii timing parameters C ksz8041nl ............................................................................................................... 49 table 13. rmii timing parameters C ksz8041rnl ............................................................................................................. 49 table 14. auto - negotiation fast link pulse (flp) timing parameters ................................................................................ 50 table 15. mdc/mdio timing parameters ............................................................................................................................ 51 table 16. power - up/reset timing parameters .................................................................................................................... 52 table 17. transformer selection criteria .............................................................................................................................. 55 table 18. qualified single port magnetics ............................................................................................................................ 55 table 19. typical reference crystal characteristics ............................................................................................................ 55 downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 9 revision 1.5 pin configuration ? ksz8041nl 32 - pin 5mm 5mm qfn downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 10 revision 1.5 pin description ? ksz8041nl pin number pin n ame type ( 2 ) pin function 1 gnd gnd ground. 2 vddpll_1.8 p 1.8v analog v dd decouple with 1.0f and 0.1f capacitors to ground. 3 vdda_3.3 p 3.3v analog v dd . 4 rx - i/o physical receive or transmit signal ( - differential). 5 rx+ i/o physical receive or transmit signal (+ differential). 6 tx - i/o physical transmit or receive signal ( - differential). 7 tx+ i/o physical transmit or receive signal (+ differential). 8 xo o crystal feedback . this pin is used only in mii mode when a 25mhz crystal is used. this pin is a no connect if oscillator or external clock source is used, or if rmi i mode is selected. 9 xi / refclk i crystal / oscillator / external clock input: mii mode: 25mhz 50ppm (crystal, osci llator, or external clock) rmii m ode: 50mhz 50ppm (oscillator, or external clock only) 10 rext i/o set physical transmit output current. connect a 6.49k ? resistor in parallel with a 100pf capacitor to ground on this pin. see ksz8041nl reference schematics. 11 mdio i/o management interface (mii) data i/o this pin requires an external 4.7k ? pull - up resistor. 12 mdc i management interface (mii) clock input this pin is synchronous to the mdio data interface . 13 rxd3 / phyad0 ipu/o mii mode: receive data output[3] ( 3 ) /. config mode: the pull - up/pull - down value is latched as phyaddr[0] during power - up / reset. see strapping options ? ksz8041nl for details. 14 rxd2 / phyad1 ipd/o mii mode: receive data output[2] ( 3 ) / config mode: the pull - up/pul l- down value is latched as phyaddr[1] during power - up / reset. see strapping options ? ksz8041nl for details. notes: 2. p = power supply. gnd = ground. i = input. o = output. i/o = bi - directional. ipd = input with internal pull - down (40k +/ - 30%). ipu = input with internal pull - up (40k +/ - 30%). opu = output with internal pull - up (40k +/ - 30%). ipu/o = input with internal pull - up (40k +/ - 30%) during power - up /reset; output pin otherwise. ipd/o = input with internal pull - down (40k +/ - 30%) during power - up/reset; output pin otherwise. 3. mii rx mode: the rxd[3..0] bits are synchronous with rxclk. when rxdv is asserted, rx d[3..0] presents valid data to mac through the mii. rxd[3..0] is invalid when rxdv is de - asserted. 4. rmii rx mode: the rxd[1:0] bits are synchronous with ref_clk. for each clock period in whi ch crs_dv is asserted, two bits of recovered data are sent from the phy. 5. mii tx mode: the t xd[3 ..0] bits a re synchronous with t xclk. when txen is asserted, t xd[3..0] presents valid data from the mac through the mii. t xd[3..0] has no effect when txen is de - asserted. 6. rmii tx mode: the txd[1:0] bits are synchronous with ref_clk. for each clock peri od in which tx_en is asserted, two bits of data are received by the phy from the mac. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 11 revision 1.5 pin description ? ksz8041nl (continued) pin number pin n ame type ( 2 ) pin function 15 rxd1 / rxd[1] / phyad2 ipd/o mii mode: receive data output[1] ( 3 ) /. rmii mode: receive data output[1] ( 4 ) /. config mode: the pull - up/pull - down value is latched as phyaddr[2] during power - up / reset. see strapping options ? ksz8041nl for details. 16 rxd0 / rxd[0] / duplex ipu/o mii mode: receive data output[0] ( 3 ) /. rmii mode: receive data output[0] ( 4 ) /. config mode: latched as duplex (register 0h, bit 8) during power - up / reset. see strapping options ? ksz8041nl for details. 17 vddio_3.3 p 3.3v digital v dd . 18 rxdv / crsdv / config2 ipd/o mii mode: receive data valid output /. rmii mode: carrier sense/receive data valid output /. config mode: the pull - up/pull - down value is latched as config2 during power - up / reset. see strapping options ? ksz8041nl for details. 19 rxc o mii mode: receive clock output . 20 rxer / rx_er / iso ipd/o mii mode: receive error output. rmii mode: receive error output. config mode: the pull - up/pull - down value is latched as isolate during power - up / reset. see str apping options ? ksz8041nl for details. 21 intrp opu interrupt output: programmable interrupt output register 1bh is the interrupt control/status register for programming the interrupt conditions and reading the interrupt status. register 1fh bit 9 sets the interrupt out put to active low (default) or active high. 22 txc o mii mode: transmit clock output . 23 txen / tx_en i mii mode: transmit enable input / . rmii mode: transmit enable i nput . 24 txd0 / txd[0] i mii mode: transmit data input[0] ( 5 ) /. rmii mode: transmit data input[0] (6) . 25 txd1 / txd[1] i mii mode: transmit data input[1] ( 5 ) /. rmii mode: transmit data input[1] (6) . 26 txd2 i mii mode: transmit data input[2] ( 5 ) /. 27 txd3 i mii mode: transmit data input[3] ( 5 ) /. 28 col / config0 ipd/o mii mode: collision detect output / . config mode: the pull - up/pull - down value is latched as config0 during power - up / reset. see strapping options ? ksz8041nl for details. 29 crs / config1 ipd/o mii mode: carrier sense output / . config mode: the pull - up/pull - down value is latched as config1 during power - up / reset. see strapping options ? ksz8041nl for details. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 12 revision 1.5 pin description ? ksz8041nl (continued) pin number pin n ame type ( 2 ) pin function 30 led0 / nwayen ipu/o led output: programmable led0 output /. config mode: latched as auto - negotiation enable (register 0h, bit 12) during power - up / reset. see strapping options ? ksz8041nl for details. the led0 pin is programmable via register 1eh bits [15:14], and is defined as follows: led mode = [00] link/activity pin state led definition no link h off link l on activity toggle blinking led mode = [01] link pin state led definition no link h off link l on led mode = [10] reserved led mode = [11] reserved downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 13 revision 1.5 pin description ? ksz8041nl (continued) pin number pin n ame type ( 2 ) pin function 31 led1 / speed ipu/o led output: programmable led1 output / config mode: latched as speed (register 0h, bit 13) during power - up / reset. see strapping options ? ksz8041nl for details. the led1 pin is programmable via register 1eh bits [15:14], and is defined as follows: led mode = [00] sp eed pin state led definition 10bt h off 100bt l on led mode = [01] activity pin state led definition no activity h off activity toggle blinking led mode = [10] reserved. led mode = [11] reserved. 32 rst# i chip reset (active low). paddle gnd gnd ground. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 14 revision 1.5 strapping options ? ksz8041nl pin strap - ins are latched during power - up or reset. in some systems, the mac receive input pins may drive hi gh during power - up or reset, and consequently cause the phy strap - in pins on the mii/rmii signals to be latched high. in this case, it is recommended to add 1k pull - downs on these phy strap - in pins to ensure the phy does not strap - in to isolate mode, or is not configured with an incorrect phy address. pin number pin n ame type ( 7 ) pin function 15 14 13 phyad2 phyad1 phyad0 ipd/o ipd/o ipu/o the phy address is latched at power - up / reset and is configurable to any value from 1 to 7. the default phy address is 00001. phy address bits [4:3] are always set to 00. 18 29 28 config2 config1 config0 ipd/o ipd/o ipd/o the config[2:0] strap - in pins are latched at power - up / reset and are defined as follows: config[2:0] mode 000 mii (default) 001 rmii 010 reserved C not used 011 reserved C not used 100 mii 100mbps preamble restore 101 reserved C not used 110 reserved C not used 111 reserved C not used 20 iso ipd/o isolate mode : pull- up = enable pull- down (default) = disable during power - up / reset, this pin value is latched into register 0h bit 10. 31 speed ipu/o speed mode: pull- up (default) = 100mbps pull- down = 10mbps during power - up / reset, this pin value is latched into register 0h bit 13 as the speed select, and also is latched into register 4h (auto - negotiation advertisement) as the speed capab ility support. 16 duplex ipu/o duplex mode: pull- up (default) = half duplex pull- down = full duplex during power - up / reset, this pin value is latched into register 0h bit 8 as the duplex mode. 30 nwayen ipu/o nway auto - negotiation enable pull- up (default) = enable auto - negotiation pull- down = disable auto - negotiation during power - up / reset, this pin value is latched into register 0h bit 12. note: 7. ipu/o = input with internal pull - up (40k +/ - 30%) during power - up/reset; output pin otherwise. ipd/o = input with internal pull - down (40k +/ - 30%) during power - up/reset; output pin otherwise. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 15 revision 1.5 pin configuration ? ksz8041rnl 1 led0 /nwayen config1 intrp led1 /speed rx_er /iso mdio mdc phyad0phyad1 rxd1 / phyad2 rxd0 / duplex vddio_3.3 crs_dv / config2 ref_clk gnd vddpll_1.8 vdda_3.3 rx- tx- tx+ xi rext rx+ xo rst# txd0 tx_en nc ncnc txd1 config0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 paddle ground (on bottom of chip) 32 - pin 5mm 5mm qfn downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 16 revision 1.5 pin description ? ksz8041rnl pin number pin n ame type ( 8 ) pin function 1 gnd gnd ground. 2 vddpll_1.8 p 1.8v analog v dd . decouple with 1.0f and 0.1f capacitors to ground. 3 vdda_3.3 p 3.3v analog v dd . 4 rx - i/o physical receive or transmit signal ( - differential). 5 rx+ i/o physical receive or transmit signal (+ differential). 6 tx - i/o physical transmit or receive signal ( - differential). 7 tx+ i/o physical transmit or receive signal (+ differential). 8 xo o crystal feedback C for 25mhz crystal . this pin is a no connect if oscillator or external clock source is used. 9 xi i crystal / oscillator / external clock input. 25mhz 50ppm . 10 rext i/o set physical transmit output current . connect a 6.49k ? resistor in parallel with a 100pf capacitor to ground on this pin. see ksz8041rnl reference schematics. 11 mdio i/o management interface (mii) data i/o . this pin requires an external 4.7k ? pull - up resistor. 12 mdc i management interface (mii) clock inpu t. this pin is synchronous to the mdio data interface . 13 phyad0 ipu/o the pull - up/pull - down value is latched as phyaddr[0] during power - up / reset. see strapping options ? ksz8041rnl for details. 14 phyad1 ipd/o the pull - up/pull - down value is latched as phyaddr[1] during power - up / reset. see strapping options ? ksz8041rnl for details. 15 rxd1 / phyad2 ipd/o rmii mode: rmii receive data output[1] ( 9 ) / config m ode: the pull - up/pull - down value is latched as phyaddr[2] during power - up / reset. see strapping options ? ksz8041rnl for details. 16 rxd0 / duplex ipu/o rmii mode: rmii receive data output[0] ( 9 ) / config mode: latched as duplex (register 0h, bit 8) during power - up / reset. see strapping options ? ksz8041rnl for details. notes: 8. p = power supply. gnd = ground. i = input. o = output. i/o = bi - directional. opu = output with internal pull - up (40k 30%). ipu/o = input with internal pull - up (40k 30%) during power - up/reset; output pin otherwise. ipd/o = input with internal pull - down (40k 30%) during power - up/reset; output pin otherwise. 9. rmii rx mode: the rxd[1:0] bits are synchronous with ref_clk. for each clock period in whi ch crs_dv is asserted, two bits of recovered data are sent from the phy. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 17 revision 1.5 pin description ? ksz8041rnl (continued) pin number pin n ame type ( 8 ) pin function 17 vddio_3.3 p 3.3v digital v dd 18 crs_dv / config2 ipd/o rmii mode: carrier sense/receive data valid output / . config mode: the pull - up/pull - down value is latched as config2 during power - up / reset. see strapping options ? ksz8041rnl for details. 19 ref_clk o 50mhz clock output . this pin provides the 50mhz rmii reference clock output to the mac. 20 rx_er / iso ipd/o rmii mode: rmii receive error output / config mode: the pull - up/pull - down value is latched as isolate during power - up / reset. see strapping options ? ksz8041rnl for details. 21 intrp opu interrupt output: programmable interrupt output . register 1bh is the interrupt control/status register for programming the interru pt conditions and reading the interrupt status. register 1fh bit 9 sets the interrupt out put to active low (default) or active high. 22 nc o no connect. 23 tx_en i rmii transmit enable input . 24 txd0 i rmii transmit data input[0] ( 10 ) . 25 txd1 i rmii transmit data input[1] ( 10 ) . 26 nc i no connect. 27 nc i no connect. 28 config0 ipd/o the pull - up/pull - down value is latched as config0 during power - up / reset. see strapping options ? ksz8041rnl for details. 29 config1 ipd/o the pull - up/pull - down value is latched as config1 during power - up / reset. see strapping options ? ksz8041rnl for details. note: 10. rmii tx mode: the txd[1:0] bits are synchronous with ref_clk. for each clock peri od in which tx_en is asserted, two bits of data are received by the phy from the mac. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 18 revision 1.5 pin description ? ksz8041rnl (continued) pin number pin n ame type ( 8 ) pin function 30 led0 / nwayen ipu/o led output: programmable led0 output /. config mode: latched as auto - negotiation enable (register 0h, bit 12) during power - up / reset. see strapping options ? ksz8041rnl for details. the led0 pin is programmable via register 1eh bits [15:14], and is defined as follows: led mode = [00] link/activity pin state led definition no link h off link l on activity toggle blinking led mode = [01] link pin state led definition no link h off link l on led mode = [10] , [11] reserved. 31 led1 / speed ipu/o led output: programmable led1 output / . config mode: latched as speed (register 0h, bit 13) during power - up / reset. see strapping options ? ksz8041rnl for details. the led1 pin is programmable via register 1eh bits [15:14], and is defined as follows: led mode = [00] speed pin state led definition 10bt h off 100bt l on led mode = [01] activity pin state led definition no activity h off activity toggle blinking led mode = [10], [11] reserved . 32 rst# i chip reset (active low) . paddle gnd gnd ground . downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 19 revision 1.5 strapping options ? ksz8041rnl pin strap - ins are latched during power - up or reset. in some systems, the mac receive input pins may drive hi gh during power - up or reset, and consequently cause the phy strap - in pins on the rmii signals to be latched high. in this case, it is recommended to add 1k pull - downs on th ese phy strap - in pins to ensure the phy does not strap - in to isolate mode, or is not configured with an incorrect phy address. pin number pin n ame type (1) pin function 15 14 13 phyad2 phyad1 phyad0 ipd/o ipd/o ipu/o the phy address is latched at power - up / reset and is configurable to any value from 1 to 7. the default phy address is 00001. phy address bits [4:3] are always set to 00. 18 29 28 config2 config1 config0 ipd/o ipd/o ipd/o the config[2:0] strap - in pins are latched at power - up / reset and are defined as follows: config[2:0] mode 000 reserved C not used 001 rmii 010 reserved C not used 011 reserved C not used 100 reserved C not used 101 reserved C not used 110 reserved C not used 111 reserved C not used 20 iso ipd/o isolate mode : pull- up = enable pull- down (default) = disable during power - up / reset, this pin value is latched into register 0h bit 10. 31 speed ipu/o speed mode: pull- up (default) = 100mbps pull- down = 10mbps during power - up / reset, this pin value is latched into register 0h bit 13 as the speed select, and also is latched into register 4h (auto - negotiation ad vertisement) as the speed capab ility support. 16 duplex ipu/o duplex mode: pull- up (default) = half duplex pull- down = full duplex during power - up / reset, this pin value is latched into register 0h bit 8 as the duplex mode. 30 nwayen ipu/o nway auto - negotiation enable : pull- up (default) = enable auto - negotiation pull- down = disable auto - negotiation during power - up / reset, this pin value is latched into register 0h bit 12. note: 11. ipu/o = input with internal pull - up (40k +/ - 30%) during power - up/reset; output pin otherwise. ipd/o = input with internal pull - down (40k +/ - 30%) during power - up/reset; output pin otherwise. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 20 revision 1.5 functional description t he ksz8041nl is a single 3.3v supply fast ethernet transceiver. it is fully compliant with the ieee 802.3u specification. on the media side, the ksz8041nl supports 10base - t and 100base - tx with hp auto mdi/mdi - x for reliable detection of and correction for straight - through and crossover cables. the ksz8041nl offers a choice of mii or rmii data interface connection with the ma c processor. the mii management bus option gives the mac processor complete access to the ksz8041nl control and status registers. a dditionally, an interrupt pin eliminates the need for the processor to poll for phy status change. physical signal transmission and reception are enhanced through the use of patented analog cir cuitries that make the design more efficient and allow for lower power consumption and smaller chip die size. the ksz8041rnl is an enhanced rmii version of the ksz8041nl that does not require a 50mhz system clock. it uses a 25mhz crystal for its input reference clock and outputs a 50mhz rmii reference clock to the mac. 1 00base - tx transmit the 100base - tx transmit function performs parallel - to - serial conversion, 4b/5b coding, scrambling, nrz - to - nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel - to - serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding, follow ed by a scrambler. the serialized data is further converted from nrz - to - nrzi format, and then transmitted in mlt3 current output. the output current is set by an external 6.49k ? 1% resistor for the 1:1 transformer ratio. it has typical rise/fall times of 4 ns and complies with the ansi tp - pmd standard regarding amplitude balance, overshoot and timing jitter. the wave - shaped 10base - t output drivers are also incorporated into the 100base - tx drivers. 100base - tx receive the 100base - tx receiver function performs adaptive equalization, dc restoration, mlt3 - to - nrzi conversion, data and clock recovery, nrzi - to - nrz conversion, de - scrambling, 4b/5b decoding, and serial - to - parallel conversion. the receiving side starts with the equalization filter to compensate for inter - symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the cable length, the e qualizer must adjust its characteristics to optimize performance. in this design, the variable equalizer makes an ini tial estimation based on comparisons of incoming signal strength against some known cable characteristics, and th en tunes itself for optimization. this is an ongoing process and self - adjusts against environmental changes such as temperature variations. next, the equalized signal goes through a dc restoration and data conversion block. the dc r estoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. t he differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this signal is sent through the de - scrambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the mii format and provided as the input data t o the mac. pll clock synthesizer the ksz8041nl/rnl generates 125 m z , 25m z and 20m z clocks for system timing. internal clocks are generated from an external 25mhz crystal or oscillator. for the ksz8041nl in rmii mode, these intern al clocks are generated from an external 50mhz oscillator or system clock. scrambler/de - scrambler (100base - tx only) the purpose of the scrambler is to spread the power spectrum of the signal in order to reduce emi and baseline wander. 10base - t transmit the 10base - t drivers are incorporated with the 100base - tx drivers to allow for transmission using the same magnetic. the drivers also perform internal wave - shaping and pre - emphasize, and output 10base - t signals with a typical amplitude of 2.5v peak. the 10base - t signals have harmonic contents that are at least 27db below the fundamental frequenc y when driven by an all - ones manchester - encoded signal. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 21 revision 1.5 10base - t receive on the receive side, input buffer and level detecting squelch circuits are employed. a differentia l input receiver circuit an d a pll performs the decoding function. the manchester - en coded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400 mv or wi th short pulse widths to prevent noise at the rx+ and rx - inputs from falsely trigger the decoder. when the input exceeds the squelch l imit, the pll locks onto the incoming signal and the ksz8041nl/rnl decodes a data frame. the receive clock is kept active duri ng idle periods in between data reception. sqe and jabber function (10base - t only) in 10base - t operation, a short pulse is put out on the col pin after each frame is transmitted. this sqe test is required as a test of the 10base - t transmit/receive path. if transmit enable (txen) is high for more than 20 ms (jabbering), the 10base - t transmitter is disabled and col is asserted high. if txen is then driven low f or more than 250 ms, the 10base - t transmitter is re - enabled and col is de - asserted (returns to low). auto - negotiation the ksz8041nl/rnl conforms to the auto - negotiation protocol, defined in clause 28 of the ieee 802.3u specification. auto - negotiation is enabled by either hardware pin strapping (pin 30) or software (register 0h bit 1 2). auto - negotiation allows unshielded twisted pair (utp) link partners to select the highest comm on mode of operation. link partners advertise their capabilities to each other, and then compare their own capabilities with those they received from their link partners. the highest speed and duplex setting that is common to the tw o link partners is selected as the mode of operation. the following list shows the speed and duplex operation mode from highest to lowest. ? priority 1: 100base - tx, full - duplex ? priority 2: 100base - tx, half - duplex ? priority 3: 10base - t, full - duplex ? priority 4: 10base - t, half - duplex if auto - negotiation is not supported or the ksz8041nl/rnl link partner is forced to bypass auto - negotiation, the ksz8041nl/rnl sets its operating mode by observing the signal at its r eceiver. this is known as parallel detection, and allows the ksz8041nl/rnl to establish link by listening for a fixed signal protocol in t he absence of auto - negotiation advertisement protocol. the auto - negotiation link up process is shown in the flow chart illustrated as figure 1 . downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 22 revision 1.5 start auto negotiation force link setting listen for 10base -t link pulses listen for 100base - tx idles attempt auto negotiation link mode set bypass auto negotiation and set link mode link mode set ? parallel operation join flow n o yes yes no figure 1 . auto - negotiation flow chart downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 23 revision 1.5 mii management (miim) interface the ksz8041nl/rnl supports the ieee 802.3 mii management interface, also known as t he management data input / output (mdio) interface. this interface allows upper - layer devices to monitor and control the state of the ksz8041nl/rnl. an external device with miim capability is used to read the phy status and/or configure the phy settings. further details on the miim interface can be found in clause 22.2.4 of the ieee 802.3 specificat ion. the miim interface consists of the following: ? a physical connection that incorporates the clock line (mdc) and the data line (mdio). ? a specific protocol that operates across the aforementioned physical connection that allows a external controller to communicate with one or more phy devices. each ksz8041nl/rnl device is assigned a unique p hy address between 1 and 7 by its phyad[2:0] strapping pins. also, every ksz8041nl/rnl dev ice supports the broadcast phy address 0, as defined per the ieee 802.3 specification, which can be used to read/write to a si ngle ksz8041nl/rnl device, or write to multiple ksz8041nl/rnl devices simultaneously. ? a set of 16 - bit mdio registers. register [0:6] are required, and their functions are defined per the ieee 802.3 specification. the additional registers are provided for expanded functionality. table 1 shows the mii management frame format for the ksz8041nl/rnl. table 1 . mii management frame format preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1s 01 10 00aaa rrrrr z0 dddddddd_dddddddd z write 32 1s 01 01 00aaa rrrrr 10 dddddddd_dddddddd z interrupt (intrp) intrp (pin 21) is an optional interrupt signal that is used to inform the external cont roller that there has been a status update to the ksz8041nl/rnl phy register. bits[15:8] of register 1bh are the interrupt control bits, and are used to enable and disable the conditions for asserting the intrp signal. bits[7:0] of register 1bh are the interrupt status bits, and are used to indicate which interrupt conditions have occurred. the interrupt statu s bits are cleared after reading register 1bh. bit 9 of register 1fh sets the interrupt level to active high or active low. mii data interface (ksz8041nl only) the media independent interface (mii) is specified in clause 22 of the ieee 802.3 sp ecification. it provides a common interface between physical layer and mac layer devices, and has the following key c haracteristics: ? supports 10mbps and 100mbps data rates. ? uses a 25mhz reference clock, sourced by the phy. ? provides independent 4 - bit wide (nibble) transmit and receive data paths. ? contains two distinct groups of signals: one for transmission and the other for reception. by default, the ksz8041nl is configured to mii mode after it is power - up or reset with the following: ? a 25mhz crystal connected to xi, xo (pins 9, 8), or an external 25mhz clock source (oscil lator) connected to xi. ? config[2:0] (pins 18, 29, 28) set to 000 (default setting). downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 24 revision 1.5 mii signal definition (ksz8041nl only) table 2 describes the mii signals. refer to clause 22 of the ieee 802.3 specification for detail ed information. table 2 . mii signal definition mii signal name direction (with respect to p hy , ksz8041nl signal ) direction (with respect to mac) description txc output input transmit clock (2.5mhz for 10mbps; 25mhz for 100mbps) txen input output transmit enable txd[3:0] input output transmit data [3:0] rxc output input receive clock (2.5mhz for 10mbps; 25mhz for 100mbps) rxdv output input receive data valid rxd[3:0] output input receive data [3:0] rxer output input, or (not required) receive error crs output input carrier sense col output input collision detection transmit clock (txc) txc is sourced by the phy. it is a continuous clock that provides the timing reference for t xen and txd[3:0]. txc is 2.5mhz for 10mbps operation and 25mhz for 100mbps operation. transmit enable (txen) txen indicates the mac is presenting nibbles on txd[3:0] for transmission. it is as serted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitt ed are presented on the mii, and is negated prior to the first txc following the final nibble of a frame. txen tran sitions synchronously with respect to txc. transmit data [3:0] (txd[3:0]) txd[3:0] transitions synchronously with respect to txc. when txen is asserted, txd [3:0] are accepted for transmission by the phy. txd[3:0] is 00 to indicate idle when txen is de - as serted. values other than 00 on txd[3:0] while txen is de - asserted are ignored by the phy. receive clock (rxc) rxc provides the timing reference for rxdv, rxd[3:0], and rxer. ? in 10mbps mode, rxc is recovered from the line while carrier is active. rxc is derived f rom the phys reference clock when the line is idle, or link is down. ? in 100mbps mode, rxc is continuously recovered from the line. if link is down, rxc is derived fr om the phys reference clock. rxc is 2.5mhz for 10mbps operation and 25mhz for 100mbps operation. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 25 revision 1.5 receive data valid (rxdv) rxdv is driven by the phy to indicate that the phy is presenting recovered and decoded nibb les on rxd[3:0]. ? in 10mbps mode, rxdv is asserted with the first nibble of the sfd (start of frame delimit er), 5d, and remains asserted until the end of the frame. ? in 100mbps mode, rxdv is asserted from the first nibble of the preamble to the last nibble of the fra me. rxdv transitions synchronously with respect to rxc. receive data [3:0] (rxd[3:0]) rxd[3:0] transitions synchronously with respect to rxc. for each clock period in which rxdv is asser ted, rxd[3:0] transfers a nibble of recovered data from the phy. receive error (rxer) rxer is asserted for one or more rxc periods to indicate that a symbol error (e.g. a coding error that a phy is capable of detecting, and that may otherwise be undetectable by the mac sub - layer) was detected somewhere in the frame presently being transferred from the phy. rxer transitions synchronously with respect to rxc. while rxdv is de - asse rted, rxer has no effect on the mac. carrier sense (crs) crs is asserted and de - asserted as follows: ? in 10mbps mode, crs assertion is based on the reception of valid preambles. crs de - assertion is based on the reception of an end - of - frame (eof) marker. ? in 100mbps mode, crs is asserted when a start - of - stream delimiter, or /j/k symbol pair is detected. crs is de - asserted when an end - of - stream delimiter, or /t/r symbol pair is detected. additionally, the pma layer de - asserts crs if idle symbols are received without /t/r. collision (col) col is asserted in half - duplex mode whenever the transmitter and receiver are simultaneously active on t he line. this is used to inform the mac that a collision has occurred during its transmission to the phy. col transitions asynchronously with respect to txc and rxc. reduced mii (rmii) data interface the reduced media independent interface (rmii) specifies a low pin count media independent interface (mii). i t provides a common interface between physical layer and mac layer devices, and has the following key characteristics: ? supports 10mbps and 100mbps data rates. ? uses a 50mhz reference clock. ? provides independent 2 - bit wide (di - bit) transmit and receive data paths. ? contains two distinct groups of signals: one for transmission and the other for reception. the ksz8041nl is configured in rmii mode after it is power - up or reset with the following: ? a 50mhz reference clock connected to refclk (pin 9). ? config[2:0] (pins 18, 29, 28) set to 001. the ksz8041rnl is configured in rmii mode and outputs the 50mhz rmii reference clock to the mac on ref_c lk (pin 19) after it is power - up or reset with the following: ? a 25mhz crystal connected to xi (pin 9) and xo (pin 8), or a 25mhz reference clock connected to xi (pin 9) . ? config[2:0] (p ins 18, 29, 28) set to 001. in rmii mode, unused mii signals, txd[3:2] (pins 27, 26), are tied to ground. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 26 revision 1.5 rmii signal definition table 3 and table 4 describe the rmii signals for ksz8041nl and ksz8041rnl. refer to rmii specification for detaile d information. table 3 . rmii signal description C ksz8041nl rmii signal name direction (with respect to p hy , ksz8041nl signal ) direction (with respect to mac) description ref_clk input input, or output synchronous 50 mhz clock reference for receive, transmit and control inter face tx_en input output transmit enable txd[1:0] input output transmit data [1:0] crs_dv output input carrier sense/receive data valid rxd[1:0] output input receive data [1:0] rx_er output input, or (not required) receive error table 4 . rmii signal description C k sz8041rnl rmii signal name direction (with respect to p hy , ksz8041rnl signal ) direction (with respect to mac) description ref_clk output input synchronous 50 mhz clock reference for receive, transmit and control interface tx_en input output transmit enable txd[1:0] input output transmit data [1:0] crs_dv output input carrier sense/receive data valid rxd[1:0] output input receive data [1:0] rx_er output input, or (not required) receive error reference clock (ref_clk) ref_clk is a continuous 50mhz clock that provides the timing reference for tx_en, txd[1:0], crs_dv, rxd[1:0], and rx_er. the ksz8041nl inputs the 50mhz ref_clk from the mac or system board. the ksz8041rnl generates the 50mhz rmii ref_clk and outputs it to the mac. transmit enable (tx_en) tx_en indicates that the mac is presenting di - bits on txd[1:0] for transmission. it is asserted synchronously with the first nibble of the preamble and remains asserted while all di - bits to be transmitted are presented on the rmii, and is negated prior to the first ref_clk following the final di - bit of a frame. tx_en transitions synchronously with respect to ref_clk. transmit data [1:0] (txd[1:0]) txd[1:0] transitions synchronously with respect to ref_clk. when tx_en is assert ed, txd[1:0] are accepted for transmission by the phy. txd[1:0] is 00 to indicate idle when tx_en is de - asserted. values other than 00 on txd[1:0] while tx_en is de - asserted are ignored by the phy. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 27 revision 1.5 carrier sense /receive data valid (crs_dv) crs_dv is asserted by the phy when the receive medium is non - idle. it is asserted asynchronously on detection of carrier. this is when squelch is passed in 10mbps mode, and when 2 non - contiguous zeroes in 10 bits are detected i n 100mbps mode. loss of carrier results in the de - assertion of crs_dv. so long as carrier detection criteria are met, crs_dv remains asserted continuously fr om the first recovered di - bit of the frame through the final recovered di - bit, and it is negated prior to the first ref_clk that follows the fin al di - bit. the data on rxd[1:0] is considered valid once crs_dv is asserted. however, since the assertion of crs_d v is asynchronous relative to ref_clk, the data on rxd[1:0] is "00" until proper receive signal deco ding takes place. receive data [1:0] (rxd[1:0]) rxd[1:0] transitions synchronously to ref_clk. for each clock period in which crs_dv is asserted, rxd[1:0] transfers two bits of recovered data from the phy. rxd[1:0] is "00" to indicate idle when crs_dv i s de - asserted. values other than 00 on rxd[1:0] while crs_dv is de - asserted are ignored by the mac. receive error (rx_er) rx_er is asserted for one or more ref_clk periods to indicate that a s ymbol error (e.g. a coding error that a phy is capable of detecting, and that may otherwise be undetectable by the mac sub - layer) was detected somewhere in the frame presently being transferred from the phy. rx_er transitions synchronously with respect to ref_clk. while crs_d v is de - asserted, rx_er has no effect on t he mac. collision detection the mac regenerates the col signal of the mii from tx_en and crs_dv. rmii signal diagram the ksz8041nl rmii pin connections to the mac are shown in figure 2 . rmii mac ksz8041nl crs_dv rxd[1:0] rx_er ref_clk crs_dvrx_er rxd[1:0] tx_en txd[1:0] tx_entxd[1:0] refclk 50 mhz osc figure 2 . ksz8041nl rmii interface downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 28 revision 1.5 the ksz8041rnl rmii pin connections to the mac are shown in figure 3 . rmii mac ref_clk ksz8041rnl crs_dv rxd[1:0] rx_er ref_clk crs_dvrx_er rxd[1:0] tx_en txd[1:0] tx_entxd[1:0] xo xi 25 mhz xtal 22 pf 22 pf figure 3 . ksz8041rnl rmii interface hp auto mdi/mdi -x hp auto mdi/mdi - x configuration eliminates the confusion of whether to use a straight cable or a crossover cable between the ksz8041nl/rnl and its link partner. this feature allows the ksz8041nl/r nl to use either type of cable to connect with a link partner that is in either mdi or mdi - x mode. the auto - sense function detects transmit and receive pairs from the link partner, and then assigns transmit and receive pairs of the ksz8041nl/rnl accord ingly. hp auto mdi/mdi - x is enabled by default. it is disabled by writing a one to register 1f bit 13. mdi and mdi - x mode is selected by register 1f bit 14 if hp auto mdi/mdi - x is disabled. an isolation transformer with symmetrical transmit and receive data paths is recomm ended to support auto mdi/mdi - x. the ieee 802.3 standard defines mdi and mdi - x as in table 5 : table 5 . mdi/mdi - x pin description mdi mdi -x rj - 45 pin signal rj - 45 pin signal 1 td+ 1 rd+ 2 td - 2 rd - 3 rd+ 3 td+ 6 rd - 6 td - downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 29 revision 1.5 straight cable a straight cable connects a mdi device to a mdi - x device, or a mdi - x device to a mdi device. figure 4 depicts a typical straight cable connection between a nic card (mdi) and a switch, or hub (mdi - x). figure 4 . typical straight cable connection crossover cable a crossover cable connects a mdi device to another mdi device, or a md i - x device to another mdi - x device. figure 5 depicts a typical crossover cable connection between two switches or hubs (two mdi - x devices). figure 5 . typical crossover cable connection receive pair transmit pair receive pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair modular connector (rj-45) nic straight cable 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch) receive pair receive pair transmit pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch) modular connector (rj-45) hub (repeater or switch) crossover cable downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 30 revision 1.5 power management the ksz8041nl/rnl offers the following power - management modes: power saving mode this mode is used to reduce power consumption when the cable is unplugged. it is in effect w hen auto - negotiation mode is enabled, cable is disconnected, and register 1f bit 10 is set to 1. under power saving m ode, the ksz8041nl/rnl shuts down all transceiver blocks, except for transmitter, energy detect and pll cir cuits. additionally, for the ksz8041nl in mii mode, the rxc clock output is disabled. rxc clock is enabled after the cable is connec ted and link is established. power - saving mode is disabled by writing a zero to register 1f bit 10. power - down mode this mode is used to power down the entire ksz8041nl/rnl device when it is not in use. p ower down mode is enabled by writing a one to register 0 bit 11. in the power down state, the ksz8041nl/rnl disables all internal functions, except for the mii management interface. reference clock connection options a crystal or clock source, such as an oscillator, is used to provide the reference clock for the ksz8041nl/rnl. figure 6 illustrates how to connect the 25mhz crystal and oscillator reference clock. figure 6 . 25mhz crystal/oscillator reference clock for the ksz8041nl, figure 7 illustrates how to connect the 50mhz oscillator reference cloc k for rmii mode. figure 7 . 50mhz oscillator reference clock fo r ksz8041nl rmii mode downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 31 revision 1.5 reference circuit for power and ground connections the ksz8041nl/rnl is a single 3.3v supply device with a built - in 1.8v low - noise regulator. the power and ground connections are shown in figure 8 and table 6 . 17 vddio_3.3 ksz8041nl/rnl vddpll_1.8 0.1uf 1.0uf v in gnd v out ` 1.8v low noise regulator (integrated) 1 3.3v 3 vdda_3.3 ferrite bead paddle 2 0.1uf 22uf ` 0.1uf 22uf ` figure 8 . ksz8041nl/rnl power and ground connections table 6 . ksz8041nl/rnl power pin description power pin pin number description vddpll_1.8 2 decouple with 1.0uf and 0.1uf capacitors to ground. vdda_3.3 3 connect to boards 3.3v supply through ferrite bead. vddio_3.3 17 connect to boards 3.3v supply. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 32 revision 1.5 register map register number (hex) description 0h basic control 1h basic status 2h phy identifier 1 3h phy identifier 2 4h auto- negotiation advertisement 5h auto- negotiation link partner ability 6h auto- negotiation expansion 7h auto- negotiation next page 8h link partner next page ability 9h C 13h reserved 14h mii control 15h rxer counter 16h C 1ah reserved 1bh interrupt control/status 1ch C 1dh reserved 1eh phy control 1 1fh phy control 2 downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 33 revision 1.5 register description address name description mode ( 12 ) default register 0h C basic control 0.15 reset 1 = s oftware reset 0 = n ormal operation this bit is self - cleared after a 1 is written to it. rw/sc 0 0.14 loop - back 1 = l oop - back mode 0 = n ormal operation rw 0 0.13 speed select (lsb) 1 = 100mbps 0 = 10mbps this bit is ignored if auto - negotiation is enabled (register 0.12 = 1). rw set by speed strapping pin. see strapping options section for details. 0.12 auto- negotiation enable 1 = e nable auto - negotiation process 0 = d isable auto - negotiation process if enabled, auto - negotiation result overrides settings in register 0.13 and 0.8. rw set by nwayen strapping pin. see strapping options ? ksz8041nl and strapping options ? ksz8041rnl sections for details. 0.11 power down 1 = p ower - down mode 0 = n ormal operation rw 0 0.10 isolate 1 = e lectrical isolation of phy from mii and tx+/tx - 0 = n ormal operation rw set by iso strapping pin. s ee strapping options ? ksz8041nl and strapping options ? ksz8041rnl sections for details. register 0h C basic control 0.9 restart auto - negotiation 1 = r estart auto - negotiation process 0 = n ormal operation. this bit is self - cleared after a 1 is written to it. rw/sc 0 0.8 duplex mode 1 = full - duplex 0 = half - duplex rw inverse of duplex strapping pin value. see strapping options ? ksz8041nl and strapping options ? ksz8041rnl sections for details. 0.7 collision test 1 = e nable col test 0 = d isable col test rw 0 0.6:1 reserved ro 000_000 0.0 disable transmitter 0 = e nable transmitter 1 = d isable transmitter rw 0 note: 12. rw = read/write. ro = read only. sc = self - cleared. lh = latch high. ll = latch low. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 34 revision 1.5 register description (continued) address name description mode ( 12 ) default register 1h C basic status 1.15 100 base - t4 1 = t4 capable 0 = not t4 capable ro 0 1.14 100 base - tx full duplex 1 = c apable of 100mbps full - duplex 0 = n ot capable of 100mbps full - duplex ro 1 1.13 100 base - tx half duplex 1 = c apable of 100mbps half - duplex 0 = n ot capable of 100mbps half - duplex ro 1 1.12 10 base - t full duplex 1 = c apable of 10mbps full - duplex 0 = n ot capable of 10mbps full - duplex ro 1 1.11 10 base - t half duplex 1 = c apable of 10mbps half - duplex 0 = n ot capable of 10mbps half - duplex ro 1 1.10:7 reserved ro 0000 1.6 no preamble 1 = p reamble suppression 0 = n ormal preamble ro 1 1.5 auto- negotiation complete 1 = a uto - negotiation process completed 0 = a uto - negotiation process not completed ro 0 1.4 remote fault 1 = r emote fault 0 = n o remote fault ro/lh 0 1.3 auto- negotiation ability 1 = c apable to perform auto - negotiation 0 = n ot capable to perform auto - negotiation ro 1 1.2 link status 1 = l ink is up 0 = l ink is down ro/ll 0 1.1 jabber detect 1 = j abber detected 0 = j abber not detected (default is low) ro/lh 0 1.0 extended capability 1 = s upports extended capabilities registers ro 1 register 2h C phy identifier 1 2.15:0 phy id number assigned to the 3 rd through 18 th bits of the organizationally unique identifier (oui). kendin communications oui is 0010a1 (hex) ro 0022h downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 35 revision 1.5 register description (continued) address name description mode ( 12 ) default register 3h C phy identifier 2 3.15:10 phy id number assigned to the 19 th through 24 th bits of the organizationally unique identifier (oui). kendin communications oui is 0010a1 (hex) ro 0001_01 3.9:4 model number six bit manufacturers model number ro 01_0001 3.3:0 revision number four bit manufacturers revision number ro indicates silicon revision register 4h C auto - negotiation advertisement 4.15 next page 1 = n ext page capable 0 = n o next page capability. rw 0 4.14 reserved ro 0 4.13 remote fault 1 = r emote fault supported 0 = n o remote fault rw 0 4.12 reserved ro 0 4.11: 10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric & symmetric pause rw 00 4.9 100base - t4 1 = t4 capable 0 = no t4 capability ro 0 4.8 100base - tx full - duplex 1 = 100mbps full - duplex capable 0 = n o 100mbps full - duplex capability rw set by speed strapping pin. see strapping options ? ksz8041nl and strapping options ? ksz8041rnl sections for details. 4.7 100base - tx half - duplex 1 = 100mbps half - duplex capable 0 = n o 100mbps half - duplex capability rw set by speed strapping pin. see strapping options ? ksz8041nl and strapping options ? ksz8041rnl sections for details. 4.6 10base - t full - duplex 1 = 10mbps full - duplex capable 0 = n o 10mbps full - duplex capability rw 1 4.5 10base - t half - duplex 1 = 10mbps half - duplex capable 0 = n o 10mbps half - duplex capability rw 1 4.4:0 selector field [00001] = ieee 802.3 rw 0_0001 downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 36 revision 1.5 register description (continued) address name description mode ( 12 ) default register 5h C auto - negotiation link partner ability 5.15 next page 1 = n ext page capable 0 = n o next page capability ro 0 5.14 acknowledge 1 = l ink code word received from partner 0 = l ink code word not yet received ro 0 5.13 remote fault 1 = r emote fault detected 0 = n o remote fault ro 0 5.12 reserved ro 0 5.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric & symmetric pause ro 00 5.9 100 base - t4 1 = t4 capable 0 = no t4 capability ro 0 5.8 100 base - tx full - duplex 1 = 100mbps full - duplex capable 0 = n o 100mbps full - duplex capability ro 0 5.7 100 base - tx half - duplex 1 = 100mbps half - duplex capable 0 = n o 100mbps half - duplex capability ro 0 5.6 10 base - t full - duplex 1 = 10mbps full - duplex capable 0 = n o 10mbps full - duplex capability ro 0 5.5 10 base - t half - duplex 1 = 10mbps half - duplex capable 0 = n o 10mbps half - duplex capability ro 0 5.4:0 selector field [00001] = ieee 802.3 ro 0_0001 downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 37 revision 1.5 register description (continued) address name description mode ( 12 ) default register 6h C auto - negotiation expansion 6.15:5 reserved ro 0000_0000_000 6.4 parallel detection fault 1 = f ault detected by parallel detection 0 = n o fault detected by parallel detection. ro/lh 0 6.3 link partner next page able 1 = l ink partner has next page capability 0 = l ink p artner does not have next page capability ro 0 6.2 next page able 1 = l ocal device has next page capability 0 = l ocal device does not have next page ca pability ro 1 6.1 page received 1 = n ew page received 0 = n ew page not received yet ro/lh 0 6.0 link partner auto - negotiation able 1 = l ink partner has auto - negotiation capability 0 = l ink partner does not have auto - negotiation capability ro 0 register 7h C auto - negotiation next page 7.15 next page 1 = a dditional next page(s) will follow 0 = l ast page rw 0 7.14 reserved ro 0 7.13 message page 1 = m essage page 0 = u nformatted page rw 1 7.12 acknowledge2 1 = w ill comply with message 0 = c annot comply with message rw 0 7.11 toggle 1 = p revious value of the transmitted link code word equaled logic one 0 = l ogic zero ro 0 7.10:0 message field 11 - bit wide field to encode 2048 messages rw 000_0000_0001 downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 38 revision 1.5 register description (continued) address name description mode ( 12 ) default register 8h C link partner next page ability 8.15 next page 1 = a dditional next page(s) will follow 0 = l ast page ro 0 8.14 acknowledge 1 = s uccessful receipt of link word 0 = n o successful receipt of link word ro 0 8.13 message page 1 = m essage page 0 = u nformatted page ro 0 8.12 acknowledge2 1 = a ble to act on the information 0 = n ot able to act on the information ro 0 8.11 toggle 1 = p revious value of transmitted link code word equal to logic zero 0 = p revious value of transmitted link code word equal to logic one ro 0 8.10:0 message field ro 000_0000_0000 register 14h C mii control 14 .15 :8 reserved ro 0000_0000 14 .7 100base - tx preamble restore 1 = restore received preamble to mii output (random latency) 0 = consume 1 - byte preamble before sending frame to mii output for fixed latency rw 0 or 1 (if config[2:0] = 100) see strapping options ? ksz8041nl and strapping options ? ksz8041rnl sections for details. 14 .6 10base - t preamble restore 1 = restore received preamble to mii output 0 = remove all 7 - bytes of preamble before sending frame (starting with sfd) to mii output rw 0 14. 5:0 reserved ro 00_0001 register 15h C rxer counter 15.15:0 rxer counter r eceive error counter for symbol error frames ro/sc 0000h downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 39 revision 1.5 register description (continued) address name description mode ( 12 ) default register 1bh C interrupt control/status 1b.15 jabber interrupt enable 1 = enable jabber interrupt 0 = disable jabber interrupt rw 0 1b.14 receive error interrupt enable 1 = enable receive error interrupt 0 = disable receive error interrupt rw 0 1b.13 page received interrupt enable 1 = enable page received interrupt 0 = disable page received interrupt rw 0 1b.12 parallel detect fault interrupt enable 1 = enable parallel detect fau lt interrupt 0 = disable parallel detect fault interrupt rw 0 1b.11 link partner acknowledge interrupt enable 1 = enable link partner acknowledge interrupt 0 = di sable link partner acknowledge interrupt rw 0 1b.10 link down interrupt enable 1= enable link down interrupt 0 = disable link down interrupt rw 0 1b.9 remote fault interrupt enable 1 = enable remote fault interrupt 0 = disable remote fault interrupt rw 0 1b.8 link up interrupt enable 1 = enable link up interrupt 0 = disable link up interrupt rw 0 1b.7 jabber interrupt 1 = jabber occurred 0 = jabber did not occurred ro/sc 0 1b.6 receive error interrupt 1 = receive error occurred 0 = receive error did not occurred ro/sc 0 1b.5 page receive interrupt 1 = page receive occurred 0 = page receive did not occurred ro/sc 0 1b.4 parallel detect fault interrupt 1 = parallel detect fault occurred 0 = parallel detect fault did not occurred ro/sc 0 1b.3 link partner acknowledge interrupt 1= link partner acknowledge occurred 0= link partner acknowledge did not occurred ro/sc 0 1b.2 link down interrupt 1= link down occurred 0= link down did not occurred ro/sc 0 1b.1 remote fault interrupt 1= remote fault occurred 0= remote fault did not occurred ro/sc 0 1b.0 link up interrupt 1= link up occurred 0= link up did not occurred ro/sc 0 downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 40 revision 1.5 register description (continued) address name description mode ( 12 ) default register 1eh C phy control 1 1e:15:14 led mode [00] = led1 : speed led0 : link/activity [01] = led1 : activity led0 : link [10] , [11] = reserved rw 00 1e.13 polarity 0 = polarity is not reversed 1 = polarity is reversed ro 1e.12 reserved ro 0 1e.11 mdi/mdi - x state 0 = mdi 1 = mdi -x ro 1e:10:8 reserved 1e:7 remote loopback 0 = n ormal mode 1 = r emote (analog) loop back is enable rw 0 1e:6:0 reserved register 1fh C phy control 2 1f:15 hp_mdix 0 = micrel auto mdi/mdi - x mode 1 = hp auto mdi/mdi - x mode rw 1 1f:14 mdi/mdi - x select when auto mdi/mdi - x is disabled, 0 = mdi mode transmit on tx+/ - (pins 7, 6) and receive on rx+/ - (pins 5, 4) 1 = mdi - x mode transmit on rx+/ - (pins 5,4) and receive on tx+/ - (pins 7, 6) rw 0 1f:13 pair s wap disable 1 = d isable auto mdi/mdi -x 0 = e nable auto mdi/mdi -x rw 0 1f.12 energy detect 1 = p resence of signal on rx+/ - ana log wire pair 0 = n o signal detected on rx+/ - ro 0 1f.11 force link 1 = f orce link pass 0 = n ormal link operation this bit bypasses the control logic and allow transmitter to send pattern even if there is no link. rw 0 downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 41 revision 1.5 register description (continued) address name description mode ( 12 ) default register 1fh C phy control 2 (continued) 1f.10 power saving 1 = e nable power saving 0 = d isable power saving if power saving mode is enabled and the cable is disconnected, the rxc clock output (in mii mode) is disabled. rxc clock is enabled after the cable is connected and link is established. rw 0 1f.9 interrupt level 1 = i nterrupt pin active high 0 = i nterrupt pin active low rw 0 1f.8 enable jabber 1 = e nable jabber counter 0 = d isable jabber counter rw 1 1f.7 auto- negotiation complete 1 = a uto - negotiation process completed 0 = a uto - negotiation process not completed rw 0 1f.6 enable pause (flow control) 1 = f low control capable 0 = n o flow control capability ro 0 1f.5 phy isolate 1 = phy in isolate mode 0 = phy in normal operation ro 0 1f.4:2 operation mode indication [000] = still in auto - negotiation [001] = 10 base - t half - duplex [010] = 100 base - tx half - duplex [011] = reserved [101] = 10 base - t full - duplex [110] = 100 base - tx full - duplex [111] = reserved ro 000 1f.1 enable sqe test 1 = e nable sqe test 0 = d isable sqe test rw 0 1f.0 disable data scrambling 1 = d isable scrambler 0 = e nable scrambler rw 0 downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 42 revision 1.5 absolute maximum ratings ( 13 ) supply voltage (v ddpll_1.8 ) .............................................. ? 0.5v to +2.4v (v ddio_3.3, v dda_3.3 ) .................................. ? 0.5v to +4.0v input voltage (all inputs) .............................. ? 0.5v to +4.0v output voltage (all outputs) .......................... - 0.5v to +4.0v lead temperature (soldering, 10s) ............................ 260c storage temperature (t s ) ......................... ? 55c to +150c esd rating ( 15 ) ................................................................ 6kv operating ratings ( 14 ) supply voltage (v ddio_3.3, v dda_3.3 ) .......................... +3.135v to +3.46 5v ambient temperature (t a , commercial ) ...................................... 0c to +70c (t a , industrial) ....................................... - 40c to +85c (t a , automotive qualified ) ..................... - 40c to +85c maximum junction temperature (t j maximum ) ........ 125c maximum case temperature (t c maximum) ............. 150c thermal resistance ( ja ) ......................................... 34c/w thermal resistance ( jc ) ........................................... 6c/w electrical characteristics ( 16 ) symbol parameter condition min . typ . max . units supply current ( 17 ) i dd1 100base - tx chip only (no transformer); full - duplex traffic @ 100% utilization 53.0 ma i dd2 10base -t chip only (no transformer); full - duplex traffic @ 100% utilization 38.0 ma i dd3 power - saving mode ethernet cable disconnected (reg. 1f.10 = 1) 32.0 ma i dd4 power - down mode software power - down (reg. 0.11 = 1) 4.0 ma ttl inputs v ih input high voltage 2.0 v v il input low voltage 0.8 v i in input current v in = gnd ~ vddio - 10 10 a ttl outputs v oh output high voltage i oh = ? 4ma 2.4 v v ol output low voltage i ol = 4ma 0.4 v |i oz | output tri - state leakage 10 a led outputs i led output drive current each led pin (led0, led1) 8 ma notes: 13. exceeding the absolute maximum rating may damage the device. stresses greater than the absolute maximum rating may cause perm anent damage to the device. operation of the device at these or any other conditions above those specified i n the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. 14. the device is not guaranteed to function outside its operating rating. 15. devices are esd se nsitive. handling precautions recommended. human body model, 1.5k ? in series with 100pf. 16. t a = 25 c. specification for packaged product only. 17. current consumption is for the single 3.3v supply ksz8041nl/rnl device only, and includes the 1. 8v supply voltage ( v ddpll_1.8 ) that is provided by the ksz8041nl/rnl. the phy ports transformer consumes an additional 45ma @ 3.3v for 100b ase - tx and 70ma @ 3.3v for 10base -t. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 43 revision 1.5 electrical characteristics ( 16 ) (continued) symbol parameter condition min . typ . max . units 100base - tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 ? termination across differential output 0.95 1.05 v v imb output voltage imbalance 100 ? termination across differential output 2 % t r , t f rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion + 0.25 ns overshoot 5 % v set reference voltage of iset 0.65 v output jitter peak - to - peak 0.7 1.4 ns 10base - t transmit (measured differentially after 1:1 transformer) vp peak differential output voltage 100 ? termination across differential output 2.2 2.8 v jitter added peak - to - peak 3.5 ns tr, tf rise/fall time 25 ns 10base - t receive vsq squelch threshold 5mhz square wave 400 mv downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 44 revision 1.5 timing diagrams figure 9 . mii sqe timing (10base - t) table 7. mii sqe timing (10base - t) parameters timing parameter description min . typ . max . unit t p txc period 400 ns t wl txc pulse width low 200 ns t wh txc pulse width high 200 ns t sqe col (sqe) delay after txen de - asserted 2.5 us t sqep col (sqe) pulse duration 1.0 us downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 45 revision 1.5 mii transmit timing (10base - t) figure 10 . mii transmit timing (10base - t) table 8 . mii transmit timing (10base - t) parameters timing parameter description min . typ . max . unit t p txc period 400 ns t wl txc pulse width low 200 ns t wh txc pulse width high 200 ns t su1 txd[3:0] setup to rising edge of txc 10 ns t su2 txen setup to rising edge of txc 10 ns t hd1 txd[3:0] hold from rising edge of txc 0 ns t hd2 txen hold from rising edge of txc 0 ns t crs1 txen high to crs asserted latency 160 ns t crs2 txen low to crs de - asserted latency 510 ns downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 46 revision 1.5 mii receive timing (10base - t) figure 11 . mii receive timing (10base - t) table 9 . mii receive timing (10base - t) parameters timing parameter description min . typ . max . unit t p rxc period 400 ns t wl rxc pulse width low 200 ns t wh rxc pulse width high 200 ns t od (rxd[3:0], rxer, rxdv) output delay from rising edge of rxc 182 225 ns t rlat crs to (rxd[3:0], rxer, rxdv) latency 6.5 us downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 47 revision 1.5 mii transmit timing (100base - tx) figure 12 . mii transmit timing (100base -tx) table 10 . mii transmit timing (100base - tx) parameters timing parameter description min . typ . max . unit t p txc period 40 ns t wl txc pulse width low 20 ns t wh txc pulse width high 20 ns t su1 txd[3:0] setup to rising edge of txc 10 ns t su2 txen setup to rising edge of txc 10 ns t hd1 txd[3:0] hold from rising edge of txc 0 ns t hd2 txen hold from rising edge of txc 0 ns t crs1 txen high to crs asserted latency 34 ns t crs2 txen low to crs de - asserted latency 33 ns downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 48 revision 1.5 mii receive timing (100base - tx) figure 13 . mii receive timing (100base -tx) table 11 . mii receive timing (100base - tx) parameters timing parameter description min . typ . max . unit t p rxc period 40 ns t wl rxc pulse width low 20 ns t wh rxc pulse width high 20 ns t od (rxd[3:0], rxer, rxdv) output delay from rising edge of rxc 19 25 ns t rlat crs to rxdv latency 140 ns crs to rxd[3:0] latency 52 ns crs to rxer latency 60 ns downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 49 revision 1.5 rmii timing figure 14 . rmii timing C data received from rmii figure 15 . rmii timing C data input to rmii table 12 . rmii timing parameters C ksz8041nl timing parameter description min . typ . max . u nit t cyc clock cycle 20 ns t 1 setup time 4 ns t 2 hold time 2 ns t od output delay 3 9 ns table 13 . rmii timing parameters C ksz8041rnl timing parameter description min . typ . max . unit t cyc clock cycle 20 ns t 1 setup time 4 ns t 2 hold time 1 ns t od output delay 9 11 13 ns downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 50 revision 1.5 auto - negotiation timing figure 16 . auto - negotiation fast link pulse (flp) timing table 14 . auto - negotiation fast link pulse (flp) timing parameters timing parameter description min . typ . max . units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulse per flp burst 17 33 downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 51 revision 1.5 mdc/mdio timing figure 17 . mdc/mdio timing table 15 . mdc/mdio timing parameters timing parameter description min . typ . max . unit t p mdc period 400 ns t 1 md1 mdio (phy input ) setup to rising edge of mdc 10 ns t md2 mdio (phy input ) hold from rising edge of mdc 4 ns t md3 mdio (phy output ) delay from rising edge of mdc 222 ns downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 52 revision 1.5 power - up/ reset timing the ksz8041nl/rnl reset timing requirement is summarized in the following figure and table. figure 18 . power - up/ reset timing table 16 . power - up/ reset timing parameters parameter description min max units t vr supply voltage (v ddio _3.3 , v dda_3.3 ) rise time 250 s t sr stable supply voltage to reset high 10 ms t cs configuration setup time 5 ns t ch configuration hold time 5 ns t rc reset to strap- in pin output 6 ns the supply voltage ( v ddio _3.3 and v dda_3.3 ) power - up waveform should be monotonic. the 250 s minimum rise time is from 10% to 90%. after the de - assertion of reset, it is recommended to wait a minimum of 100 s before starting programming on the miim (mdc/mdio) interface. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 53 revision 1.5 reset circuit the reset circuit in figure 19 is recommended for powering up the ksz8041nl/rnl if reset is triggered by the power supply. ksz8041nl/rnl 3.3v d1 d1 : 1n 4148 r 10k c 10 uf rst # figure 19 . recommended reset circuit the reset circuit in figure 20 is recommended for applications where reset is driven by another device (e.g., cpu or fpga). at power - on - reset, r, c and d1 provide the necessary ramp rise time to reset the ksz80 41nl/rnl device. the rst_out_n from cpu/fpga provides the warm reset after power - up. ksz 8041 nl / rnl cpu / fpga 3.3v c 10 uf r 10k rst _ out _n d1 d2 d1 , d2 : 1n 4148 rst # figure 20 . recommended reset circuit for interfacing with cpu/fpga reset output. downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 54 revision 1.5 reference circuits for led strapping pins the figure 21 shows the reference circuits for pull - up, float and pull - down on the led1 and led0 strapping pins. led pin 220? 4.7? 3.3v 1 ? pull-up ksz8041nl/rnl 220? 3.3v float ksz8041nl/rnl led pin 220? 3.3v pull-down ksz8041nl/rnl led pin figure 21 . reference circuits for led strapping pins downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 55 revision 1.5 selection of isolation transformer a 1:1 isolation transformer is required at the line interface. an isolation transformer wi th integrated common - mode chokes is recommended for exceeding fcc requirements. table 17 gives recommended transformer characteristics. table 17 . transformer selection criteria parameter value test condition turns ratio 1 ct : 1 ct open - circuit inductance (minimum) 350 h 100mv, 100khz, 8ma leakage inductance (maximum) 0.4 h 1mhz (minimum) inter - winding capacitance (typical) 12pf dc resistance (typical) 0.9 ? insertion loss (maximum) ? 1.0db 0mhz C 65mhz hipot (minimum) 1500vrms table 18 . qualified single port magnetics magnetic manufacturer part number auto mdi -x number of port bel fuse s558 - 5999 - u7 yes 1 bel fuse (mag jack) si- 46001 yes 1 bel fuse (mag jack) si- 50170 yes 1 delta lf8505 yes 1 lankom lf - h41s yes 1 pulse h1102 yes 1 pulse (low cost) h1260 yes 1 transpower hb726 yes 1 tdk (mag jack) tla - 6t718 yes 1 selection of reference crystal table 19 . typical reference crystal characteristics chara cteristics value units frequency 25 mhz frequency tolerance (maximum) 50 ppm load capacitance 20 pf series resistance 40 ? downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 56 revision 1.5 package information and recommended landing pattern ( 8 ) 32 -pin 5mm 5mm qfn note: 18. package information is correct as of the publication date. for updates and most current i nformation, go to www.micrel.com . downloaded from: http:///
micrel, inc. ksz8041nl/rnl february 4, 2015 57 revision 1.5 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.com micrel, inc. is a leading global manufacturer of ic solutions for the worldwide high performance l inear and power, lan, and timing & communications markets. the companys products include advanced mixed - signal, analog & power semiconductors; high - performance communication, clock management, mems - based clock oscillators & crystal - less clock generators, ethe rnet switches, and physical layer transceiver ics. company customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and comp uter products. corporation headquarters and state - of - the - art wafer fa brication facilities are located in san jose, ca, with regional sales and support off ices and advanced technology design centers situated throughout the americas, europe, and asia. additionally, the company maintains an extensive network of distributors a nd reps worldwide. micrel makes no representations or warranties with respect to the accuracy or completenes s of the inf ormation furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. e xcep t as provided in micrels terms and conditions of sale for such products, micrel assumes no liabil ity whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of mi crel products including liability or warranties rela ting to fitness for a particular purpose, merchantability, or infringement of any patent , copyright , or other intellectual property right. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or sy stems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to r esult in a significant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or s ystems is a purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 20 06 micrel, incorporated. downloaded from: http:///

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